1. Field of the Invention
The present invention relates to processes for the formation of cobalt salicide layers during semiconductor device fabrication and, in particular, to such processes that include a sputter etch surface preparation step prior to a cobalt layer deposition step.
2. Description of the Related Art
In Metal-Oxide-Semiconductor (MOS) device manufacturing, self-aligned metal silicide layers (also known as "salicide" layers) are useful in reducing the sheet resistance of polysilicon interconnections, source regions and drain regions, as well as contact resistance. See, for example, Stanley Wolf, Silicon Processing for the VLSI Era, Vol. I, 388-399 (Lattice Press, 1986).
FIGS. 1-3 illustrate a conventional process for forming a metal silicide layer over a polysilicon gate, a source region and a drain region of an MOS transistor structure. A conventional MOS transistor structure 10 includes a gate oxide layer 12 overlying P-type silicon substrate 14 between N-type drain region 16 and N-type source region 18, both of which are formed in the P-type silicon substrate 14. A conventional MOS transistor structure 10 also includes a polysilicon gate 20 overlying the gate oxide layer 12, as well as shallow trench isolation regions 22. The shallow trench isolation regions 22 isolate the MOS transistor structure 10 from neighboring semiconductor device structures (not shown). Gate sidewall spacers 24, typically formed of silicon dioxide or silicon nitride, are disposed on the lateral surfaces of the polysilicon gate 20 and the gate oxide layer 12.
In a conventional metal silicide layer formation process, a metal layer 28 (typically a titanium layer) is deposited over an MOS transistor structure 10, as illustrated in FIG. 2. Wherever metal layer 28 is in contact with silicon surfaces (i.e. source region 18, drain region 16 and polysilicon gate 20), the metal therein is thermally reacted to form a metal silicide layer. The metal silicide layer formation conditions, such as temperature and gaseous ambient, are selected to foster the reaction of the metal layer with silicon surfaces, while impeding reaction of the metal layer with silicon dioxide or silicon nitride surfaces (i.e. the gate sidewall spacers 24 and shallow trench isolation regions 22). A selective etch is then used to remove unreacted metal from the surfaces of the gate sidewall spacers 24 and shallow trench isolation regions 22, as well as any unreacted metal residue remaining above the source region 18, drain region 16 and polysilicon gate 20. The etch is "selective" since it does not remove the metal silicide layer that was formed on the silicon surfaces. The resultant structure, as illustrated in FIG. 3, includes metal silicide layers 32, 34 and 36 covering the drain region 16, the source region 18 and the polysilicon gate 20, respectively.
The use of cobalt silicide layers is becoming increasingly common in semiconductor devices as an alternative to titanium silicide layers since cobalt silicide layers provide a sheet resistance that is relatively independent of polysilicon gate line width. See, T. Yamazaki et al., 21 psec Switching 0.1 m-CMOS at Room Temperature Using High Performance Co Salicide Process, IEDM Tech. Dig., 906 (1993), which is hereby incorporated by reference. The successful formation of cobalt salicide layers on 0.065 micron polysilicon lines, as reported in Q. Z. Hong et al., CoSi.sub.2 With Low Diode Leakage and Low Sheet Resistance at 0.065um Gate Length, IEDM Tech. Dig., 107 (1997), which is hereby incorporated by reference, indicates that cobalt silicide layers will continue to be utilized in the future. Although Q. Z. Hong et al. reports the use of an in-situ Ar/H.sub.2 sputter clean prior to cobalt metal deposition, there is no description or teaching related to the effect of such an Ar sputter clean in device performance or yield.
A drawback of conventional cobalt silicide layer formation processes is the tendency to form cobalt silicide "bridges" on a gate sidewall spacer, connecting a cobalt silicide layer on a polysilicon gate with a cobalt silicide layer on a source region or drain region. The cobalt silicide bridges can result from cobalt silicide overgrowth (i.e. "creep") across the gate sidewall spacer. Such cobalt silicide bridges cause an undesirable electrical short between the polysilicon gate and the source/drain region, thereby decreasing semiconductor device fabrication yield.
In addition, since cobalt can not react with silicon through even a thin layer of native silicon dioxide that is typically present on the surfaces of source regions, drain regions and polysilicon gates, source regions, these surfaces need to be free of native silicon dioxide layers upon cobalt layer deposition. Conventional cobalt silicide formation processes, therefore, typically utilize a wet chemical cleaning step to remove native silicon dioxide layers before depositing a cobalt layer. If the queue time between such a wet chemical cleaning step and the cobalt layer deposition step is lengthy, however, a native silicon dioxide layer may reform, thereby interfering with cobalt silicide layer formation.
Needed in the art is a process for forming a self-aligned cobalt silicide layer on an MOS transistor structure that provides a reduced susceptibility to the formation of cobalt silicide bridges and is tolerant of lengthy queue times between a wet chemical clean step and a cobalt layer deposition step.